A nonvolatile semiconductor memory, such as an erasable programmable read-only memory of the UV-erasable or electrically erasable type, is a device that can retain data when power is removed from the memory. This function is performed with a group of memory-cell structures that store electronic charge. An example of the charge-storage structure is a stacked floating-gate FET in which a regular control gate is situated over an insulation-surrounded floating gate. When a voltage is applied to the control gate, charge is typically injected from the channel region of the FET onto the floating gate where the charge can be stored for a long time after the applied voltage is removed.
The floating gate must be surrounded by a dielectric film with good isolation properties to insure that the charge is retained. One type of dielectric film consists of (a) a thin oxide-nitride-oxide ("ONO") composite layer situated between the floating and control gates and (b) a thermally grown oxide on the sidewalls of the floating gate. The thin ONO layer is used not only to isolate the floating gate but also to couple high voltage from the control gate to the floating gate. The thermal oxide on the sidewalls of the floating gate is used mainly as the isolation dielectric between the two gates.
To provide good electric isolation, the sidewall oxide generally has to be grown at a fairly high temperature, usually in excess of 1050.degree. C. Also, the corners formed between the ONO and the sidewall oxide are likely to be potential weak points for charge leakage in the standard stacked-gate cell design. These concerns impose severe restrictions in scaling down memory device size. As devices are scaled down, the temperature to which they are exposed during formation must be minimized in order to insure the integrity of the thin gate oxide used in the memory cells. The high oxidation temperature required to form the sidewall oxide becomes a major concern. Furthermore, the ONO layer has to be thinned down to maintain the coupling efficiency between the control and floating gates as the gate oxide thickness is reduced. This increases the likelihood of corner leakage between the ONO layer and sidewall oxide.
Prior techniques for insulating a floating gate from a control gate in a semiconductor memory are illustrated in Sato U.S. Pat. 4,720,323. Sato discloses a first technique in which an ONO composite layer is formed along the top of the floating gate and along the sidewalls of the floating gate extending in channel-length direction. In a second technique disclosed in Sato, an ONO layer is formed along the top of the floating gate. Oxide is subsequently provided along the floating-gate sidewalls extending in the channel-length direction. In both techniques, oxide is provided along the floating-gate sidewalls extending in the channel-width direction.
Both of these techniques suffer from the previously discussed drawbacks. In the first technique, the only oxide lying on the sides of the floating gate extending in the channel-length direction is the small thickness of the lower layer of the ONO layer. This increases the likelihood of corner leakage between the floating and control gates. In the second technique, a fairly thick layer of oxide must be formed along the exposed gate sidewalls extending in the channel-length direction. Doing so normally requires that the gate oxide be exposed to high temperatures for an extended period of time which, in the case of scaled-down devices, could damage the integrity of the thin gate oxide.
What is needed in view of these drawbacks is a process by which scaled-down nonvolatile semiconductor memories can be formed without directly exposing the gates of the memory cells to excessive temperatures for extended periods of time while still enabling the floating gate in each cell to be properly isolated from the control gate.